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Chapter 1: About This MegaCore Function
MegaCore Verification
1–3
■
■
Preliminary support —Altera verifies the IP core with preliminary timing models
for this device family. The IP core meets all functional requirements, but might still
be undergoing timing analysis for the device family. You can use it in production
designs with caution.
Final support —Altera verifies the IP core with final timing models for this device
family. The IP core meets all functional and timing requirements for the device
family and can be used in production designs.
Table 1–3 shows the level of support offered by the NCO MegaCore function to each
of the Altera device families.
Table 1–2. Device Family Support
Device Family
Support
Arria ?
II GX
Final
Arria II GZ
Arria V
Final
Full
Cyclone ?
III
Final
Cyclone III LS
Cyclone IV
Stratix ? III
Stratix IV GT
Stratix IV GX/E
Stratix V
Other device families
Final
Final
Final
Final
Final
Full
No support
MegaCore Verification
Before releasing a version of the NCO MegaCore function, Altera runs comprehensive
regression tests to verify its quality and correctness.
First a custom variation of the NCO MegaCore function is created. Next, Verilog HDL
and VHDL IP functional simulation models are exercised by their appropriate
testbenches in ModelSim simulators and the results are compared to the output of a
bit-accurate model.
The regression suite covers various parameters such as architecture options,
frequency modulation, phase modulation, and precision.
November 2013
Altera Corporation
NCO MegaCore Function
User Guide
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